This application is based on Patent Application Nos. 2000-162839 filed May 31, 2000 and 2001-152716 filed May 22, 2001 in Japan, the content of which is incorporated hereinto by reference.
1. Field of the Invention
The present invention relates to an ultra-low power consumption differential type logic circuit capable of performing high-speed operation at a low power supply voltage of less than or equal to 1V.
2. Description of the Related Art
In a high-speed CMOS logic circuit such as a frequency divider or the like, high-speed operation at a decreased power supply voltage is effective in view of reduced power consumption. A conventional CMOS inverter circuit comprises an enhancement type PMOSFET and an NMOSFET.
In this circuit, in the case of being operated at a high speed with a low power supply voltage, when the amplitude of the input signal is decreased to lower than the power supply voltage, since amplification action is performed up to the power supply voltage level by the CMOS inverter circuit, this results in an increased delay time. Further, even when the amplitude of the input signal is at the power supply voltage level, a delay time due to a capacity Cm between input and output of the CMOS inverter circuit is a substantial bottleneck (for example, Douseki et al., IEICE Trans. Electron, Vol. E76-C, No. 8, pp. 1325-1332, August 1993). This is because the capacity Cm between gate and drain of the two FET constituting the CMOS inverter circuit functions as Miller effect which equivalently increases a load capacity CL and increases the delay time.
Then, to prevent the delay time from increasing, capacity between gate and drain of the FET may be reduced, however, by this technique, an addition of a specific process such as improving the device structure is required. In particular, in a SOI (Semiconductor On Insulator) device having a small load capacity, since the proportion of capacity between gate and drain in the total capacity is high, the delay time due to capacity between gate and drain substantially hinders improvement of the speed performance.
An object of the present invention is to provide a differential type logic circuit capable of achieving high-speed and low power consumption at a low power supply voltage of less than or equal to 1V.
A first aspect for solving the above problem is a differential type logic circuit comprising a differential circuit, in which the differential circuit is composed of a differential push-pull circuit comprising a depletion type MOSFET and an enhancement type MOSFET of the same polarity.
A second aspect is that, in the first aspect, an input from a differential input terminal to the enhancement type MOSFET and an output from the depletion type MOSFET of a differential output terminal are connected, and the differential push-pull circuit is constructed as a latch type.
A third aspect is that, in the first and second aspects, differential input terminals of the differential push-pull circuit are inputted through a pair of transmission gates comprising a depletion type MOSFET and driven by a clock signal.
A fourth aspect is that, in the third aspect, the differential circuit is replaced with first and second differential push-pull circuits comprising a depletion type MOSFET and an enhancement type MOSFET of the same polarity, the differential output terminal of the first differential push-pull circuit is connected to the differential input terminal of the second differential push-pull circuit through a first pair of transmission gates comprising a depletion type MOSFET and driven by a clock signal, the differential output terminal of the second differential push-pull circuit is connected to the differential input terminal of the first differential push-pull circuit through a second pair of transmission gates comprising a depletion type MOSFET and driven by a reversed clock signal which is reversed of the above clock signal.
A fifth aspect is a differential type logic circuit comprising differential circuits characterized in that the differential circuit is replaced with first and second differential push-pull circuit comprising a depletion type MOSFET and an enhancement type MOSFET of the same polarity, the differential output terminal of the first differential push-pull circuit is connected directly to the differential input terminal of the second differential push-pull circuit, the differential input terminal of the first differential push-pull circuit is inputted through a pair of transmission gates comprising a depletion type MOSFET and driven by a clock signal, and inside the second differential push-pull circuit, input from the differential input terminal to the enhancement type MOSFET and output to the differential output terminal from the depletion type MOSFET are connected, forming a latch type.
A sixth aspect is, in the fifth aspect, further comprising third and fourth differential push-pull circuits comprising a depletion type MOSFET and an enhancement type MOSFET of the same polarity, in which the differential output terminal of the second differential push-pull circuit is connected to the differential input terminal of the third differential push-pull circuit through a first pair of transmission gates comprising a depletion type MOSFET and driven by a clock signal, the differential output terminal of the third differential push-pull circuit is connected directly to the differential input terminal of the fourth differential push-pull circuit, the differential output terminal of the fourth differential push-pull circuit is connected to the differential input terminal of the first differential push-pull circuit through a second pair of transmission gates comprising a depletion type MOSFET and driven by a reversed clock signal which is reversed of the clock signal, and inside the fourth differential push-pull circuit, input from the differential input terminal to the enhancement type MOSFET and output to the differential output terminal from the depletion type MOSFET are connected, forming a latch type.
A seventh aspect is, in the first or second aspect, further comprising a CMOS inverter circuit in which the differential output terminal of the differential circuit is connected with a differential input terminal, and a threshold voltage of the MOSFET constituting the CMOS inverter circuit is set to the same as or higher than that of the enhancement type MOSFET and smaller than about xc2xd of the power supply voltage.
An eighth aspect is, in the fourth aspect, the differential output terminal of the second differential push-pull circuit is connected to a differential input terminal of the CMOS inverter pair circuit.
A ninth aspect is, in the sixth aspect, the differential output terminal of the fourth differential push-pull circuit is connected to a differential input terminal of the CMOS inverter pair circuit.
A tenth aspect is, in the seventh or eighth aspect, a CMOS logic circuit is connected at a post stage of the CMOS inverter pair circuit, a threshold voltage of MOSFET constituting the CMOS logic circuit is set higher than a threshold voltage of MOSFET constituting the CMOS inverter pair circuit.
An eleventh aspect is, in any one of the seventh to tenth aspects, power supply voltage is supplied through a power FET controlled by a sleep control signal.
A twelfth aspect is, in any one of the first to eleventh aspects, FETs constituting the circuit are those of SOI structure.
From the above description, according to the present invention, it is possible to achieve high speed and low power consumption at a low supply voltage of less than or equal to 1V.
The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments thereof taken in conjunction with the accompanying drawings.